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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16432B
1/8, 1/15 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
The PD16432B is a controller/driver with 1/8 and 1/15 duty dot matrix LCD display capability. It has 60 segment outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12 columns x 2 lines (at 1/15 duty). LED drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use in a car stereo front panel, etc.
FEATURES
* Dot matrix LCD controller/driver * Pictograph display segment drive capability (MAX. 64) * LCD driver unit power supply VLCD independently settable (MAX. 10 V) * On-chip key scan circuit (8 x 4 matrix) * Alphanumeric character and symbol display capability provided by on-chip ROM (5 x 7 dots) 240 characters + 16 user-defined characters * Display contents 1/8 duty: 13 columns x 1 line, 64 pictograph displays, 4 LEDs 1/15 duty: 12 columns x 2 lines, 60 pictograph displays, 4 LEDs * Serial data input/output (SCK, STB, DATA) * On-chip oscillator * Reduced power consumption possible using standby mode
ORDERING INFORMATION
Part Number Package 100-PIN PLASTIC TQFP (FINE PITCH, 14 x 14), Standard ROM code
PD16432BGC-001-9EU
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S11092E6V0DS00 (6th edition) Date Published December 2000 NS CP(K) Printed in Japan
The mark # shows major revised points.
(c)
1998
PD16432B
CONTENT
1. 2. 3. 4.
BLOCK DIAGRAM ............................................................................................................................. 3 PIN CONFIGURATION (Top view) .................................................................................................... 4 PIN DESCRIPTIONS........................................................................................................................... 5 PIN FUNCTION ................................................................................................................................... 6
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 LCD Display...............................................................................................................................................6 Character Codes and Character Patterns ..................................................................................................7 DISPLAY RAM ADDRESSES...................................................................................................................8 Pictograph Display RAM Addresses..........................................................................................................8 CGRAM Column Addresses .....................................................................................................................9 Configuring a Key Matrix ..........................................................................................................................10 Construction of Key Data RAM.................................................................................................................12 Key Input Equivalent Circuit......................................................................................................................12 Key Request (KEY REQ) .........................................................................................................................13
4.10 LED Output Latch Configuration..............................................................................................................13 4.11 Commands ...............................................................................................................................................14 4.12 Standby Mode...........................................................................................................................................17 4.13 SERIAL COMMUNICATION FORMATS.................................................................................................19
5. 6.
ELECTRICAL SPECIFICATIONS ................................................................................................... 20 ACCESS PROCEDURES ................................................................................................................ 29
6.1 6.2 6.3 6.4 6.5 6.6 Initialization...............................................................................................................................................29 Display Data Rewrite (Address Setting) .................................................................................................31 Key Data Read .........................................................................................................................................32 CGRAM Write ...........................................................................................................................................33 Standby (Released by Status Command) ................................................................................................34 Standby (Released by KEYn)....................................................................................................................35 Example 1 of PD16432B application circuit ..........................................................................................36 Example 2 of PD16432B application circuit ..........................................................................................37
7.
PD16432B APPLICATION CIRCUITS .......................................................................................... 36
7.1 7.2
8. 9.
PACKAGE DRAWING ...................................................................................................................... 38 RECOMMENDED SOLDERING CONDITIONS .............................................................................. 39
2
Data Sheet S11092EJ6V0DS
PD16432B
1. BLOCK DIAGRAM
SEG61/COM14 SEG65/COM10
SEG1/KS1
SEG8/KS8 SEG9
SEG60
COM9
4 LED Driver 4 4-Bit LED Output Latch 4
5
5
Segment Driver 65
5
Common Driver 15
65-Bit Output Latch 65 2
15-Bit Shift Register
65-Bit Shift Register Timing Generator Parallel/Serial Conversion 5 5 8 OSCIN CG RAM 5x7 x 16 Display Data RAM 8 x 25 OSC Character Display RAM 64 Bits OSCOUT
CG ROM 5 x 7 x 240
8
5 STB SCK DATA Serial I/F Command Decoder Key Data RAM 4x8 KEY1 8
COM0
LED1
LED4
KEY4
KEY REQ
RESET LCD OFF SYNC
VDD
VLCD
VSS
VLC1
VLC2
VLC3
VLC4
VLC5
Data Sheet S11092E6V0DS
3
PD16432B
2. PIN CONFIGURATION (Top view)
* PD16432BGC-001-9EU
SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61/COM14 SEG62/COM13 SEG63/COM12 SEG64/COM11 SEG65/COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
75 76
51 50
100 1
26 25
SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/KS8 SEG7/KS7 SEG6/KS6 SEG5/KS5 SEG4/KS4 SEG3/KS3 SEG2/KS2 SEG1/KS1
4
LED1 LED2 LED3 LED4 VSS VLC5 VLC4 VLC3 VLC2 VLC1 VLCD VDD SYNC LCD OFF RESET KEY REQ SCK DATA STB OSCIN OSCOUT KEY1 KEY2 KEY3 KEY4
Data Sheet S11092EJ6V0DS
PD16432B
3. PIN DESCRIPTIONS
Symbol SEG1/KS1 to SEG8/KS8 SEG9 to SEG60 SEG61/COM14 to SEG85/COM10 COM0 to COM9 LED1 to LED4 SCK Pin Name Segment /key source dualfunction Segment Segment /common dualfunction Common LED Shift clock 91 to 100 1 to 4 17 O O I 34 to 85 86 to 90 O O Pin No. 26 to 33 I/O O Function Pins with dual function as dot matrix LCD segment outputs and key scanning key source outputs Dot matrix LCD segment outputs Switchable to either dot matrix LCD segment outputs or common outputs Dot matrix LCD common outputs LED outputs are Nch open-drain Data shift clock. Data is read on rising edge, and output on falling edge. DATA Data 18 I/O Performs input of commands, key data, etc., and key data output. Input is performed from the MSB on the rise of the shift clock, and the first 8 bits are recognized as a command. Output is performed from the MSB on the fall of the shift clock. Output is Nch open-drain. STB Strobe 19 I Data input is enabled when "H". Command processing is performed on a fall. KEY REQ Key request 16 O "H" if there is key data, "L" if there is none. Key data can be read irrespective of the state of this pin. Output is CMOS output. RESET LCD OFF Reset LCD off 15 14 I I Initial state is set when "L". When "L", a forced LCD off operation is performed, and SEGn & COMn output the unselected waveform. SYNC Synchronization 13 I/O Synchronization signal input/output pin. When 2 or more chips are used, wired-OR connection is made to each chip. A pull-up resistor is also required when one chip is used. OSCIN Oscillation 20 I Connect oscillator resistor. When an external oscillator is used, input a clock OSCOUT 21 O signal to the OSCIN pin and leave the OSCOUT pin open, depending on the setting status of the CLS pin. KEY1 to KEY4 VDD VSS VLCD Key data Logic power supply GND LCD drive voltage LCD drive power supply 22 to 25 12 5 11 10 to 6 I - - - - Key scanning key data inputs Internal logic power supply pin GND pin LCD drive power supply pin Dot matrix LCD drive power supply. Connect VLC5 to ground when an internal oscillator is used.
#
#
VLC1 to VLC5
Data Sheet S11092E6V0DS
5
PD16432B
4. PIN FUNCTION
4.1 LCD Display In the PD16432B LCD display, a 5 x 7-segment display and pictograph display segments can be driven. The pictograph display segment common output is allocated to COM0, and up to 64 can be driven. (1) Example of 1/8 duty connections
SEG
1 2 3 4 5 6 7 8 9 10 61 62 63 64 65
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0
64 Pictograph Segments
(2) Example of 1/15 duty connections
SEG
1 2 3 4 5 6 7 8 9 10 56 57 58 59 60
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM0
60 Pictograph Segments
6
Data Sheet S11092EJ6V0DS
PD16432B
4.2 Character Codes and Character Patterns The relation between character codes and character patterns is shown below. Character codes 00H to 0FH are allocated to CGRAM. Character codes 10H to 1FH and E0H to FFH are undefined.
Higher Bits 0XH 1XH 2XH 3XH 4XH 5XH 6XH 7XH 8XH 9XH AXH BXH CXH DXH EXH FXH Lower Bits X0HRAM CG (1) CG (2) CG (3) CG (4) CG (5) CG (6) CG (7) CG (8) CG (9) CG (10) CG (11) CG (12) CG (13) CG (14) CG (15) CG (16)
X1HRAM
X2HRAM
X3HRAM
X4HRAM
X5HRAM
X6HRAM
X7HRAM
X8HRAM
X9HRAM
XAHRAM
XBHRAM
XCHRAM
XDHRAM
XEHRAM
XFHRAM
Data Sheet S11092E6V0DS
7
PD16432B
4.3 Display RAM Addresses Display RAM addresses are allocated as shown below irrespective of the display mode.
Column No. Line 1 Line 2 1 2 3 4 5 6 7 8 9 10 11 12 13
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H
4.4 Pictograph Display RAM Addresses Pictograph display RAM addresses are allocated as shown below.
Segment Output No. Address b7 00H 01H 02H 03H 04H 05H 06H 07H 1 9 17 25 33 41 49 57 b6 2 10 18 26 34 42 50 58 b5 3 11 19 27 35 43 51 59 b4 4 12 20 28 36 44 52 60 b3 5 13 21 29 37 45 53 61 b2 6 14 22 30 38 46 54 62 b1 7 15 23 31 39 47 55 63 b0 8 16 24 32 40 48 56 64
Remark When 1/15 duty is used (12 columns x 2 lines), 61 to 64 are disabled.
8
Data Sheet S11092EJ6V0DS
PD16432B
4.5 CGRAM Column Addresses A maximum of any sixteen 5 x 7-dot characters can be written in CGRAM. The row address within one character is allocated as shown below, and is specified by bits b7 to b5. The character code for which a write is to be performed must be specified beforehand with an address setting command.
Dot Data b7 0 0 0 0 1 1 1 b6 0 0 1 1 0 0 1 b5 0 1 0 1 0 1 0 b4 b3 b2 b1 b0
Row Address 00H 01H 02H 03H 04H 05H 06H
* * * * * * *
* * * * * * *
* * * * * * *
Font Data
* * * * * * *
* * * * * * *
Row Address
(5 x 7 Dots)
Remark * : Font data (1: ON, 0: OFF)
Data Sheet S11092E6V0DS
9
PD16432B
# 4.6 Configuring a Key Matrix Examples of key matrix configurations are shown below. (1) Assumed case when 3 or more keys simultaneously pressed A configuration example is shown below. In this kind of configuration, between 0 and 32 switches in the ON state can be identified.
KEY1 KEY2 KEY3 KEY4
=
KS1
KS2
KS3
KS4
KS5
KS6
KS7
KS8
(2) Assumed case when 2 or fewer keys simultaneously pressed A configuration example is shown below. In this kind of configuration, between 0 and 2 switches in the ON state can be identified.
KEY1 KEY2 KEY3 KEY4
=
Diode A
KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
10
Data Sheet S11092EJ6V0DS
PD16432B
In this example, if 3 or more keys are simultaneously pressed, switches in the OFF state may be inadvertently judged as being ON. Take, for example, the case shown below where SW2 to SW4 are ON and KS1 is selected (low level). Normally, the I1 current would flow and SW3 would be detected as being in the ON state. However, because SW2 and SW4 are ON, the I2 current flows, and SW1 is mistakenly identified as being ON.
SW1 SW2
KEY1
I2 SW3 SW4
KEY2
I1
=
KEY3 KEY4
KS1 KS2 Selected
KS3
KS4
KS5
KS6
KS7
KS8
Also, if diode A is not connected, not only will the key data be unable to be read correctly, but the LCD may also be affected and the IC damaged or its characteristics degraded. Take, for example, the case shown below where SW1 and SW2 are ON, and KS1 is selected (low level). In this case, in addition to I1, which is the current that normally flows, the short current between KS1 and KS2 (I2) also flows, potentially causing the following three problems. <1> <2> <3> Incorrect transmission of the level to KEY2 will prevent the key data from being latched properly. Because KS1 and KS2 have alternate functions as SEG outputs, the LCD will not display correctly. The flowing of the short current between KS2 (high level) and KS1 (low level) (I2) will damage or degrade the IC.
KEY1
SW1 SW2
KEY2
I1
=
KEY3 KEY4
I2
KS1
KS2
KS3
KS4
KS5
KS6
KS7
KS8
Selected (Low level)
Not selected (High level)
Data Sheet S11092E6V0DS
11
PD16432B
4.7 Construction of Key Data RAM Key data is stored as shown below, and is read in MSB-first order by a read command.
b7 KS8 KS6 KS4 KS2 b4 b3 KS7 KS5 KS3 KS1 Read Order Key data is as follows: 1: ON 0: OFF b0
KEY4 KEY3 KEY2 KEY1
4.8 Key Input Equivalent Circuit
VDD Pull-Up Control Signal
R To Key Data RAM KEYn
Remark In the event of key source output, the pull-up control signal becomes "H", and the pull-up transistor is turned on.
12
Data Sheet S11092EJ6V0DS
PD16432B
4.9 Key Request (KEY REQ) A key request is output as shown below according to the state.
State In key scan operation KEY REQ
Note
Key Scan Internal Pull-Up Resistor During key scan : ON During display : OFF Always ON
High level is output while any key Note data is "1". High level is output in case of key input only. Fixed at low level
In standby mode or when SEGn & COMn are fixed at VLC5 When key scanning is stopped
Always OFF
Note KEY REQ does not become low until the key data is all "0" (It is not synchronized with the key data reads). 4.10 LED Output Latch Configuration The low-order 4 bits of the LED output latch are enabled, and the high-order 4 bits disabled, as shown below.
MSB LSB
x
x
x
x
b3
b2
b1
b0
x : Don't Care
LED1 LED2 LED3 LED4
Latch data is as follows: 1: ON 0: OFF
Data Sheet S11092E6V0DS
13
PD16432B
4.11 Commands Commands set the display mode and status. The first byte after a rise edge on the STB pin is regarded as a command. If STB is driven low during command/data transfer, serial communication is initialized and the command/data being transferred is invalidated (However, a command or data that has already been transferred is valid). (1) Display Setting Command This command initializes the PD16432B, and sets the duty, number of segments, number of commons, master/ slave operation, and the drive voltage supply method. When multiple chips are used, only the chip that sent the command is enabled. If initialization is performed during display, the display may be affected (especially when multiple chips are used). The state set when this command is executed is: LCD off, LED on, key scanning stopped. To restart the display, it is necessary to execute "status command" normal operation. However, nothing is done if the same mode is selected.
MSB 0 0 LSB
x
x
x
b2
b1
b0
x : Don't Care
Duty setting 0: 1/8 duty (SEG61/COM14 to SEG65/COM10 segment outputs) 1: 1/15 duty (SEG61/COM14 to SEG65/COM10 common outputs) Master/slave setting Note 0: Master 1: Slave Drive voltage supply method selection 0: External 1: Internal
After powering on
x
#
x
x
0
0
0
Note Please set only one PD16432B to master, and the other to slave when in multi-chip mode. And please set to master, when in single chip mode.
14
Data Sheet S11092EJ6V0DS
PD16432B
(2) Data Setting Command Sets the data write mode, read mode, and address increment mode.
MSB 0 1 LSB
x
x
b3
b2
b1
b0
x : Don't Care
Data write mode/read mode setting 000: Write to display data RAM 001: Write to character display RAM 010: Write to CGRAM 011: Write to LED output latch 100: Read key data Address increment mode setting (Display data RAM, character display RAM) 0: Increment after data write 1: Address fixed
After powering on
x
(3) Address Setting Command
x
0
0
0
0
Sets the display data RAM or character display RAM address.
MSB 1 0 LSB
x
b4
b3
b2
b1
b0
x:
Don't Care
Address Display data RAM : 00H to 18H Character display RAM : 00H to 07H CGRAM : 00H to 0FH After powering on
x
0
0
0
0
0
Caution If an unspecified address is set, data cannot be written until a correct address is next set. The address is not incremented even in increment mode.
Data Sheet S11092E6V0DS
15
PD16432B
(4) Status Command Controls the status of the PD16432.
MSB 1 1 b5 b4 b3 b2 b1 LSB b0
LCD cotrol 00: LCD forced off (SEGn, COMn = VLC5) 01: LCD forced off (SEGn, COMn = unselected waveform) 10: Normal operation 11: Normal operation LED control 0: LED forced off 1: Normal operation Key scan control 0: Key scanning stopped 1: Key scan operation Standby mode setting 0: Normal operation 1: Standby mode Test mode setting 0: Normal operation 1: Test mode After powering on 0 0 0 0 0 0
Note2
Note1
Notes 1. The following states are use prohibited modes, and key scanning does not operate if these states are set.
0 0 0 0 1 1 0 1 0 0 0 0
#
2. The key data input operation is stopped. The key source signals from SEGn pin are output even in this state.
16
Data Sheet S11092EJ6V0DS
PD16432B
4.12 Standby Mode If standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0 of the status command. (1) LCD forced off (SEGn, COMn = VLC5) (2) LED forced off (3) Key scanning stopped (but KEYn = key input wait) (4) OSC stopped There are two ways of releasing standby mode, as follows: (a)Using Status Command (b)Using KEYn (a) Using Status Command Select normal operation with bit b4 of the status command. Table 4-1 Example of Use of Status Command
Command/Data Item Standby mode Status command STB b7 L H 1 1 0 0 0 0 0 0 Standby release (OSC oscillation start), LCD control off (SEGn, COMn = VLC5), LED forced off, key scanning stopped 10 s 1 1 0 0 1 1 1 0
Note
Description b6 b5 b4 b3 b2 b1 b0
Standby transition time Status command End
L H L
Normal operation
Note If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker.
Data Sheet S11092E6V0DS
17
PD16432B
(b) Using KEYn If any key is set to the ON state, the standby mode is released and OSC oscillation starts. Also, KEY REQ is set to "H", informing the microcomputer that a key has been pressed and standby mode has been released. In this state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after the standby transition time, and fetch the key data. Table 4-2 Example of Use of KEYn
Command/Data Item Standby mode Key data present STB b7 L L Standby release (KEY REQ = H, OSC oscillation start) 10 s 1 1 0 0 1 0 0 1
Note
Description b6 b5 b4 b3 b2 b1 b0
Standby transition time Status command
L H
LCD forced off (unselected waveform), LED forced off, key scan operation 1 frame or more
Key scan Data setting command Key data Key data Key data Key data End
L H H H H H L 0 1 0 0 0 1 0 0
Key data read, address increment For KS8, KS7 For KS6, KS5 For KS4, KS3 For KS2, KS1 Key distinction
* * * *
* * * *
* * * *
* * * *
* * * *
* * * *
* * * *
* * * *
Note
If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker.
Remark
* : key data (1:ON, 0 : OFF)
18
Data Sheet S11092EJ6V0DS
PD16432B
4.13 Serial Communication Formats (1) Reception (Command/Data Write)
If data continues
STB
DATA
b7
b6
b5
b2
b1
b0
SCK
1
2
3
6
7
8
(2) Transmission (Command/Data Read)
STB
DATA
b7
b6
b5
b2
b1
b0
b7
b6
b5
b4
b3
SCK
1
2
3
6
7
8 1 s
1
2
3
4
5
6
Data Read Command Setting
Wait Time tWAIT
Data Read
Caution As the DATA pin is an Nch open-drain output, a pull-up resistor must be connected externally (1 k to 10 k).
Data Sheet S11092E6V0DS
19
PD16432B
5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, V SS = 0 V)
Parameter Logic supply voltage Logic input voltage Logic output voltage (DOUT, LEDn) LCD drive supply voltage LCD drive power supply input voltage Driver output voltage (Segment, Common) LED drive current Package allowable dissipation Operating ambient temperature Storage temperature range IOL1 PT TA Tstg 20 1000 -40 to +85 -55 to +150 mA mW C C VOUT2 -0.3 to +VLCD + 0.3 V Symbol VDD VIN VOUT VLCD VLC1 to VLC5 Rating -0.3 to +7.0 -0.3 to +VDD + 0.3 -0.3 to +7.0 -0.3 to +12.0 -0.3 to +VLCD + 0.3 Unit V V V V V
#
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Ranges
Parameter Logic supply voltage LCD drive supply voltage Logic input voltage Driver input voltage LED drive current Symbol VDD VLCD VIN VLCD1 to VLCD5 IOL1 Conditions MIN. 2.7 VDD 0 0 TYP. 5.0 8.0 MAX. 5.5 10.0 VDD VLCD 15 Unit V V V V mA
20
Data Sheet S11092EJ6V0DS
PD16432B
Electrical Characteristics (Unless specified otherwise, TA = -40 to +85C, V VLCD = 8 V 10%)
Parameter High-level input voltage Low-level input voltage High-level input current Symbol VIH VIL IIH SCK, STB, LCDOFF, RESET, KEY1 to KEY4 Low-level input current IIL SCK, STB, LCD OFF, RESET, KEY1 to KEY4 Low-level output voltage High-level output voltage Low-level output voltage High-level leak current Low-level leak current Common output ONresistance Segment output ONresistance Current consumption (Logic) IDD2 IDD1 RSEG VOL1 VOH2 VOL2 ILOH2 ILOL2 RCOM LED1 to LED4, IOL1 = 15 mA OSCOUT, KEY REQ, IOH2 = -1 mA DATA, OSCOUT, SYNC, IOL2 = 4 mA DATA, SYNC, VIN/OUT = VDD DATA, SYNC, VIN/OUT = VSS VLCD to VLC5 COM0 to COM14, | IO | = 100 A VLCD to VLC5 SEG1 to SEG60, | IO | = 100 A Normal operation fOSC = 250 kHz Standby mode, VI = VDD or VSS, fOSC stopped Current consumption (Driver) ILCD2 ILCD1 Normal operation, internal bias selected, no load Standby mode, internal bias used, no load 5 1000 5
Note
DD
= 5 V 10%,
TYP. MAX. VDD 0.3 VDD 1 Unit V V
Conditions
MIN. 0.7 VDD 0
A A
V V
-1
1.0 0.9 VDD 0.1 VDD 1 -1 2.4
V
A A
k
4.0
k
, VI = VDD or VSS,
500
A A A A
Note Normal operation: VDD = 5 V, VLCD = 8 V
Data Sheet S11092EJ6V0DS
21
PD16432B
Switching Characreristics (Unless Specified Otherwise, TA = -40 to +85C, V RL = 5 k, CL = 150 pF)
Parameter Oscillator frequency Output data delay time Output data delay time SYNC delay time Symbol fOSC tPZL tPLZ tDSYNC R = 100 k SCK DATA SCK DATA Conditions MIN. 175
DD
= VLCD = 5 V 10%,
TYP. 250 MAX. 325 100 300 1.5 Unit kHz ns ns
s
Remarks 1. The time for one frame is found as follows. 1 frame = 1/fOSC x 128 clocks x duty number + 1/fOSC x 64 clocks If fOSC = 250 kHz and duty = 1/15, 1 frame = 4 s x 128 x 15 + 4 s x 64 = 7.94 ms 2. TYP. values are reference values for TA = 25C.
Required Timing Conditions (Unless Specified Otherwise, TA = -40 to +85C, V VLCD = 8 V 10%, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width Shift-clock cycle High-level shift clock pulse width Low-level shift clock pulse width Shift clock hold time Data setup time Data hold time STB hold time STB hold time Wait time Symbol fOSC tWHC tWLC tCYK tWHK tWLK tHSTBK tDS tDH tHKSTB tWSTB tWAIT 8th SCK 9th SCK , in data read SYNC removal time Standby transition time Reset pulse width Power-ON reset time tSREM tPSTB tWRS tPON RESET From Power-ON 250 10 0.1 4 Conditions OSCIN external clock OSCIN external clock OSCIN external clock SCK SCK SCK STB SCK DATA SCK SCK DATA SCK STB MIN. 100 1 1 900 400 400 1.5 100 200 1 1 1
DD
= 5 V 10%,
MAX. 500 5 5 Unit kHz
TYP.
s s
ns ns ns
s
ns ns
s s s
ns
s s
CLK
Output Load Circuit
VDD
5 k DATA 150 pF
22
Data Sheet S11092EJ6V0DS
PD16432B
Switching Specifications Waveform Diagrams (1/2)
1/fC tWHC
VIH OSCIN VIL tWLC
VIH STB
VIH VIL tHSTBK tHKSTB tWSTB
tCYK tWLK VIH SCK VIL tDS VIH VIL tDH tWLK
DATA
Data Sheet S11092EJ6V0DS
23
PD16432B
Switching Specification Waveform Diagrams (2/2)
SYNC Timing (Master) One Frame fOSC tDSYNC SYNC tSREM One Frame SYNC Timing (Slave) One Frame One Frame
Internal Reset
SCK VIL
tPZL
tPLZ
DATA VOL2
RESET
RESET tWRE
24
Data Sheet S11092EJ6V0DS
PD16432B
Output Waveforms
(1) 1/8 Duty (1/4 Bias: VLC2: VLC3)
* Key scan period 0 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 1 2 3 4 5 6 7 * K 0 1
COM0
COM1
COM7
VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5
SEG1
SEG2
VLCD 3/4VLCD SEG1-COM0 2/4VLCD 1/4VLCD 0 -1/4VLCD -2/4VLCD -3/4VLCD -VLCD VLCD 3/4VLCD SEG1-COM1 2/4VLCD 1/4VLCD 0 -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
512 s 4.4 ms
256 s
Data Sheet S11092EJ6V0DS
25
PD16432B
Enlargement of Key Scan Period
7 1 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 2 3 4 K 5 6 7 8 0
COM0
SEG1
SEG2
SEG8
SEG9 to SEG65
VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5
= Key source output
26
Data Sheet S11092EJ6V0DS
PD16432B
(2) 1/15 Duty (1/5 Bias)
* Key scan period * 14 K 1 2
0 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5
1
2
3
4
5
6
7
8
9
10
11
12
13
COM0 1/2VLCD
COM1 1/2VLCD
COM14 1/2VLCD
VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD
SEG1
3/5VLCD 1/2VLCD 1/5VLCD SEG1-COM0 0 -1/5VLCD -1/2VLCD -3/5VLCD -VLCD 512 s 7.9 ms 256 s
Data Sheet S11092EJ6V0DS
27
PD16432B
Enlargement of Key Scan Period
14 1 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 2 3 4 K 5 6 7 8 0
COM0 1/2VLCD
SEG1
SEG2
SEG8
VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5
SEG9 to SEG65
= Key source output
28
Data Sheet S11092EJ6V0DS
PD16432B
6. ACCESS PROCEDURES
Access procedures are illustrated below by means of flowcharts and timing charts. 6.1 Initialization (1) Flowchart
Start
Initial state initialization
Display setting command (command 1) MSB LSB 0 0 0 0 0 1 0 1 (1/15 duty, master, internal drive)
Key scan start
Status command (command 2) MSB 1 1 0 0 1 0 0
LSB 1 (LCD off, LED off, key scan operation)
Display data RAM write
Data setting command (command 3) MSB LSB 0 1 0 0 0 0 0 0 (Display data RAM, increment)
Address setting
Address setting command (command 4) MSB LSB 1 0 0 0 0 0 0 0 (Display data RAM: 0H)
Display data
All data written? YES Character display RAM write
NO
Data setting command (command 5) MSB LSB 0 1 0 0 0 0 0 1 (Character display RAM, increment)
Character data
All data written? YES
NO
Data Sheet S11092EJ6V0DS
29
PD16432B
LED output latch write Data setting command (command 6) MSB LSB 0 1 0 0 0 0 1 1 (LED latch, increment)
LED data
LCD, LED on
Status command (command 7) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK STB DATA SCK STB DATA SCK STB Data n Command 6 Data Command 7 Data n-1 Data n Command 5 Data 1 Command 1 Command 2 Command 3 Command 4 Data 1
30
Data Sheet S11092EJ6V0DS
PD16432B
6.2 Display Data Rewrite (Address Setting) (1) Flowchart
Start
Display data RAM write
Data setting command (command 1) MSB LSB 0 1 0 0 1 0 0 0 (Display data RAM, address fixed)
Address setting
Address setting command (command 2) MSB LSB 1 0 0 0 0 1 0 1 (Display data RAM: 5H)
Display data
To next processing
(2) Timing chart
DATA SCK STB Command 1 Command 2 Data
Data Sheet S11092EJ6V0DS
31
PD16432B
6.3 Key Data Read (1) Flowchart
Start
KEY REQ recognition
KEY REQ = H? YES
NO
Key data read
Data setting command (command 1) MSB LSB 0 1 0 0 0 1 0 0 (Key data)
Wait OK? YES
NO Wait time: 1 s
Key data
All data read? YES To next processing
NO
(2) Timing chart
DATA SCK STB KEY REQ Command 1 tWAIT Data 1 Data 2 Data 3
DATA SCK STB KEY REQ
Data 4
Cautions 1. Wait time tWAIT (1 s) is necessary from the rise of the 8th shift clock of command 1 until the fall of the 1st shift clock of data 1. 2. KEY REQ does not become low until the key data is all " 0" . (It is not synchronized with the key data reads.)
32
Data Sheet S11092EJ6V0DS
PD16432B
6.4 CGRAM Write (1) Flowchart
Start
CGRAM write
Data setting command (command 1) MSB LSB 0 1 0 0 0 0 1 0 (CGRAM, increment)
Address setting
Address setting command (command 2) MSB LSB 1 0 0 0 0 0 0 0 (CGRAM character code: 0H)
CGRAM data
All data written? YES To next processing
NO
(2) Timing chart
DATA SCK STB DATA SCK STB Data 6 Data 7 Command 1 Command 2 Data 1 Data 2
Data Sheet S11092EJ6V0DS
33
PD16432B
6.5 Standby (Released by Status Command) (1) Flowchart
Start
Standby
Status command (command 1) MSB 1 1 0 1 0 0 0
LSB 0 (Standby)
Standby release
Status command (command 2) MSB 1 1 0 0 0 0 0
LSB 0 (Standby release)
Transition time OK? YES
NO Standby transition time: 10 s
Normal operation
Status command (command 3) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK tSTBY STB Command 1 Command 2 Command 3
34
Data Sheet S11092EJ6V0DS
PD16432B
6.6 Standby (Released by KEYn) (1) Flowchart
Start
Standby
Status command (command 1) MSB 1 1 0 1 0 0 0
LSB 0 (Standby)
Key request
Key (KEYn) input KEY REQ = H, OSC oscillation start
Transition time OK? YES
NO Standby transition time: 10 s
Normal operation
Status command (command 2) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK tSTBY STB KEY REQ Command 1 Command 2
Data Sheet S11092EJ6V0DS
35
PD16432B
#
7. PD16432B APPLICATION CIRCUITS
7.1 Example 1 of PD16432B application circuit (With internal power supply circuit, 1/15 duty)
5V VDD to 10 V
C1 VDD R1 DATA CPU SCK STB KEYREQ LCD OFF RESET VSS VLCD VLC1 VLC2 VLC3 VLC4 VLC5 OSCIN OSCOUT LED1 LED2 LED3 LED4 SYNC KEY1 KEY2 KEY3 KEY4 R4 R2 LED R3 open
VDD
CPU or
VDD
PD16432B
EG1/KS1
EG2/KS2
15
EG9 to EG60
52
EG8/KS8
OM0 to OM14
LCD Panel
Key matrixNote (8 x 4 Keys) R1,R4 R2 R3 C1 = 1k to 10 k = 100 k = 330 to 1 k = 0.1 to 1.0 F
Note
36
Data Sheet S11092EJ6V0DS
PD16432B
7.2 Example 2 of PD16432B application circuit (With external drive circuit, 1/15 duty)
5V VDD to 10V
C1 VDD VSS
VLCD
R5 R5
VLC1 VLC2 R5 DATA SCK STB KEYREQ LCD OFF RESET OSCIN OSCOUT LED1 LED2 LED3 LED4 SYNC KEY1 KEY2 KEY3 KEY4 R4 R2 LED R3 VLC3 R5 VLC4 R5 VLC5 CPU or VDD VDD C2
R1
CPU
PD16432B
EG1/KS1 EG2/KS2
15
EG9 to EG60
52
EG8/KS8
OM0 to OM14
LCD Panel
Key matrixNote (8 x 4 Keys) R1,R4,R5 = 1k to 10 k R2 = 100 k R3 = 330 to 1 k C1 = 0.1 to 1.0 F C2 = 0.01 to 0.1 F
Note
Data Sheet S11092EJ6V0DS
37
PD16432B
8. PACKAGE DRAWING
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D Q R
100 1
26 25
F G H P I
M
J
K
N
S
L M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. S100GC-50-9EU-2
38
Data Sheet S11092EJ6V0DS
PD16432B
9. RECOMMENDED SOLDERING CONDITIONS
The PD16432B should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual(C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
PD16432BGC-001-9EU
Soldering Method
: 100-PIN PLASTIC TQFP (14 x 14)
Soldering Conditions Recommended Soldering Condition Symbol
Infrared reflow
Package peak temperature : 235C, Time : 30 sec. MAX. (at 210 or higher), Count : 3 times or less. Exposure limit: 7 days
Note
IR35-107-3
(after that, prebake at 125C for 10 hours) VP15-107-3
VPS
Package peak temperature : 235C, Time : 40 sec. MAX. (at 210 or higher), Count : 3 times or less. Exposure limit: 7 days
Note
(after that, prebake at 125C for 10 hours).
Partial heating
Pin temperature: 300C MAX., Time: 3 seconds MAX. (per side of device)
-
Note After opening the dry pack, store it at 25C ro less and 65% RH or less for the allowable storeage period. Caution Do not use different soldering methods together (except the partial heating).
Data Sheet S11092EJ6V0DS
39
PD16432B
[MEMO]
40
Data Sheet S11092EJ6V0DS
PD16432B
[MEMO]
Data Sheet S11092EJ6V0DS
41
PD16432B
[MEMO]
42
Data Sheet S11092EJ6V0DS
PD16432B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S11092EJ6V0DS
43
PD16432B
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System Semiconductor Device Mounting Technology Manual (IEI-1212) (C10535E)
* The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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